# B12X TP3 PCIe oneshot overlay

This image retains the pinned v9 vLLM base and replaces only B12X's
`distributed/pcie_oneshot.py` and `distributed/pcie_oneshot.cu`. The minimal
backport is `provisioning/patches/b12x-f3686b5-tp3-init-race.patch`. The signal
slab must be zeroed before its CUDA IPC handle is published; otherwise a fast
peer can post an arrival that a late local memset erases.

The production derivative also adds
`VLLM_PCIE_ONESHOT_ALLREDUCE_MIN_SIZE`. ai01 uses `64KB`, routing smaller
latency-sensitive reductions through NCCL while retaining B12X for 64 KiB
one-shot collectives.

The three-rank implementation must pass
`provisioning/tests/run-b12x-v9-overlay-tp3-test.sh` before promotion.